INMC 80 News

  

May-September 1981, Issue 4











Page 25 of 71











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80-BUS pin allocation

+e ee

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AUX CLK /RAM DIS /RESET SW /NAS MEM /NAS 10 /DBDR

/RESET /HALT /BAL /BAO /BUSRQ IEI IEO /NMI /INT /WAIT /RFSH /M1 /TORQ /MREQ /WR /RD AO

Al

A2

A3

AG

AS

A6

A7

A8

AQ A10 All Al2 Al3 Al4 AL5 Al6 Al? ALB GND DO

D1

D2

D3 D4

D5

D6

D7

DESCRIPTION Ground Ground Ground Ground System clock A low on this line initiates a short pulse on line 21 Reserved for future use 4MHz clock signal (optional) Ram disable Reset switch Memory decode to Nascom 1 I/O decode to Nascom 1 and 2 Data bus drive, used to change the direction of the data bus buffers on the buffer board or Supermum. 50uS reset pulse, resets entire system. Z80 halt signal DMA daisy chain Z80 bus request Interrupt daisy chain Z80 NMI line, (not used by N1) Z80 interrupt line Z80 wait line Z80 refresh signal Z80 opcode fetch signal Z80 input/output signal Z80 memory signal Z80 write signal Z80 read signal

Z80 16 bit address bus

Optional implementation for extended addressing. Ground to seperate the data and address busses.

Bidirectional data bus.


This is an OCR’d version of the scanned page and likely contains recognition errors.











Page 25 of 71