INMC 80 News

  

May–September 1981, Issue 4











Page 25 of 71











80-BUS pin allocation

PINSIGNALDESCRIPTION
1GNDGround
2GNDGround
3GNDGround
4GNDGround
5CLOCKSystem clock
6*/NMI SWA low on this line initiates a short pulse on line 21
7RSFUReserved for future use
8AUX CLK4MHz clock signal (optional)
9*/RAM DISRam disable
10*/RESET SWReset switch
11*/NAS MEMMemory decode to Nascom 1
12*/NAS IOI/O decode to Nascom 1 and 2
13*/DBDRData bus drive, used to change the direction of the data bus buffers on the buffer board or Supermum.
14*/RESET50uS reset pulse, resets entire system.
15/HALTZ80 halt signal
16/BALDMA
17/BAO  daisy chain
18/BUSRQZ80 bus request
19IEIInterrupt
20IEO  daisy chain
21*/NMIZ80 NMI line, (not used by N1)
22*/INTZ80 interrupt line
23*/WAITZ80 wait line
24/RFSHZ80 refresh signal
25/M1Z80 opcode fetch signal
26/TORQZ80 input/output signal
27/MREQZ80 memory signal
28/WRZ80 write signal
29/RDZ80 read signal
30A0
31A1
32A2
33A3
34A4
35AS
36A6
37A7
38A8Z80 16 bit
39A9  address bus
40A10
41A11
42A12
43A13
44A14
45A15
46A16Optional implementation
47A17  for extended
48A18  addressing.
49GNDGround to seperate the data and address busses.
50D0
51D1
52D2
53D3Bidirectional data bus.
54D4
55D5
56D6
57D7

This is an OCR’d version of the scanned page and likely contains recognition errors.











Page 25 of 71