58 RSFU Reserved for future use
59 INT 0 Interrupt
60 INT 1 request
61 INT 2 lines
62 INT 3
63 /PWRE Powerfail warning
64 AUX PWR Backup power
65 NDEF 1 Not to
66 NDEF 2 be defined
67 GND Ground to seperate power and signal lines.
1) * is an open collector line.
2) IEI to be linked to TEO on cards not using the interrupt daisy chain.
3) /BAI to be linked to /BAO on cards not using the DMA daisy chain.
4) Bus drivers must be able to drive 75/15 U.L.
5) Bus receivers must not load the bus past 1/0.25 U.L.
6) Bus master to pull up all open collector lines with 2k2.
7) Bus master to pull up the following lines with 10k, /HALT, /MREQ, /IORQ, /RD, /WR,
8) Bus timing reference point is pin 6 of the Z80. As the bus is in essence a buffered
Z80, the timing of bus signals is as the Zilog/Mostek Z80 data book. All 7280 signals
are buffered onto the bus with 20nS +/- 10nS buffers, the sole exception being the bus
clock which should be 20nS (+/+ 10nS) ahead of the Z80 clock (pin6). The timing of
other signals is detailed in the description of the particular signal. All expanston
card timing must, however be referenced to the bus.
9) Cards using /BAI, /BAO, IEI & IEO should pull them up with 2k2.
10) Bus termination. Long buses may require termination. 220R on each line to a 2.6V
low impedance source should solve 99% of problems.
11) Grounding. The ground line to the PSU should be as short as possible and as thick
12) The names of the various bus signals are as detailed above, please do not change
them or abbreviate them, ie AUX CLK not AUX CLOCK or A CLOCK etc.
The following is a line by line description of the bus and should help resolve any
Lines 1-4, GND.
The quality of tue system ground cannot be overemphasised. Ground noise
problems were at the root of the now infamous Nascom "Memory plague". The faster that
systems c0 the more critical the noise problem will become. Noise problems will
manifest themselves as a generally unreliable system with a predilection to do "odd"