Line 5, CLOCK.
This line is important as all the bus timing is derived from it. It should
spend at least 46% of its time below VOL (0-4V) and at least 46% of is time above VOH
(2.4V), it has the other 8% spare to go up and down. The clock on the bus should be
20nS (+/ 10nS) ahead of the clock on pin 6 of the Z80.
Line 6, /NMI SW.
Provision has been made on the bus for an NMI switch and this line is to be
held high by the bus master. Grounding it will initiate a short pulse on line 21 and
the Z80 /NMI input. Users are cautioned that switch bounce may cause more than one
Line 7, RSFU.
This line is reserved for allocation at a later date, please do not use.
Line 8, AUX CLK.
This line is a new allocation. Many boards (eg disk controllers) require a 1,
2 or 4 MHz signal. This was easily provided when the CPU clock was 2 or 4 MHz, however
the advent of the 6 MHz Z80 changes the situation. Any bus master not running at
either 2 or 4 MHz must provide a 4 MHz clock on this line. Designers of expansion
cards should take note of this and provide a link to allow the board to use this line
instead of line 5.
Line 9, /RAM DIS.
This signal is intended to prioritise memory. Normally this signal would be
generated by memory on the bus master, an EPROM card or any other high priority memory
when a memory read took place. A RAM card would normally gate /RAM DIS with the output
buffer, so that in the event of /RAM DIS being asserted the output buffer would fail
to be enabled, this would have the effect of “overlaying” RAM with EPROM/ROM. /RAM DIS
should not inhibit a write cycle; it should also remain high for any cycle apart from
a memory read.
Line 10, /RESET SW.
A high to low on this line will initiate a reset cycle. It is intended that a
switch be connected between this line and ground. The actual RESET line is line 14.
Line 11, /NAS MEM.
This signal is only used by Nascom 1 and is asserted when a Nascom memory
address is detected. It would normally be provided by a memory board and would
typically be 0000H to 0FFFH or F000H to FFFFH. This is an obsolete signal and no new
boards that require it should be designed. This line used to be called MEMEXT.
Line 12, /NAS IO.
This line used to be called IOEXT and many people persist in still calling it
that, even though the two are different. In its original form (note that it was active
high) it would be taken high to indicate an I/O address external to the Nascom, in its
current form it is taken low to indicate a Nascom I/O address, that is to say that it
looks for a Nascom I/O address as opposed to looking for an external address. /NAS IO
should be taken low within 50nS of a Nascom I/O address and /IORQ, (referenced to the
bus). In its original form the onboard ports on the Nascom would remain enabled for a
short fraction of an external I/O cycle (the time taken to detect an external address
and assert IOEXT) and this was the cause of many obscure problems. If you have
problems a good test is to write a short machine code routine to continuously write
80H to port 08H. If the breakpoint register display comes up you have a problem, if
not you don’t. /NAS IO is a obsolete signal utilised by Nascom 1 and 2 and all new
designs should incorporate full I/O decoding.