Line 13, /DBDR.
This signal is used by the Buffer board and Supermum with Nascom 1. It
controls the direction of the data bus buffers. When an expansion card outputs data to
the bus this line must be taken low, normally this is the same signal as used to turn
on the output buffers. Despite being only used by expanded Nascom 1s it is felt that
this signal must be provided on all expansion cards. While /DBDR should ideally go low
before the data bus driver is enabled, it must be low within 30nS of the data bus
driver being enabled and must release /DBDR within 30nS of the data bus drivers being
Line 14, /RESET.
This line is the “cleaned up” version of line 10. It is important that the
falling edge of the reset pulse on this line be synchronised with the falling edge of
/M1, and the bus master must provide the appropriate logic to take care of this. The
last issue of the Nasbus specification called for a 10uS reset pulse. This has now
been extended to 50uS as chips in the 179X family require a 50us pulse. Deep
investigation of the matter has yet to yield a 179X chip that can tell the difference
between a 10uS pulse and a 50uS pulse. N2 owners who are concerned by this should
substitute a 10nF capacitor for Cl (lnF). Supermum owners need not worry as this has
been taken care of.
Line 15, /HALT.
Z80 halt signal. Up to this point in time nobody has used it, but it is there.
Lines 16 17 18, /BAI /BAO /BUSRQ.
/BAI and /BAO are the DMA daisy chain. If an expansion card wishes to take
control of the bus (an expansion card is any bus card which is not a bus master) it
asserts /BUSRQ; the bus master will respond by taking /BAO low. The mother board
connects line 17 to 16 between each slot, ie line 17 of the bus master will go to 16
of the adjacent card, line 16 at the bus master is not used although it can be a test
point. Between all subsequent cards line 17 goes to line 16 (for full connection
details see the section on daisy chains). Cards that do not use the DMA facilities
should connect 17 to 16. /BAO will be fed into the /BAI of any potential DMAing
device, and the /BAO of the same device will go into the /BAI of the next and so on.
If a potential DMAing device has not asserted the /BUSRQ line it will pass on the
signal. When the signal reaches the device which originally asserted the /BUSRQ line
it will hold /BAO high, at this point it will have taken contol of the bus. The
highest priority device is that nearest the bus master.(CPU card).
Lines 19 20, IEI IEO.
Interrupt daisy chain for vectored interrupts. The IEI input of the highest
priority device is held high, the IEO output of that device goes to the IEI input of
the device with the second highest priority, the daisy chain is continued until the
device with lowest priority is reached, its IEO is not connected. It is recommended
that line 20 of the bus master is linked to line 19 of the adjacent card and so on
down the bus. As the interrupt daisy chain does not involve the Z80 it is possible to
move the bus master from slot to slot and vary the level of interrupt priority of the
devices on the bus master. The DMA daisy chain however does involve the Z80, and the
bus master must always be to one side of the expansion cards which may generate a
/BUSRQ. If the motherboard is linked in the recommended manner the device with highest
interrupt priority is nearest to the bus master. If the daisy chain is connected the
other way arround a problem could arise as the Z80-DMA can also generate interrupts.
For further details on connections see the section on daisy chains.
Line 21, /NMI.
A short pulse will be generated on this line by the bus master from a low on
line 6 (/NMI SW). On Nascom 1 the NMI is used in the single step feature and is not