Line 22, /INT.
Used for the Z80 maskable interrupt. For full details see the book “Z80 family
program interrupt structure” available from Zilog.
Line 23, /WAIT.
Used to insert wait states into Z80 machine cycles. Expansion cards that
require wait states should provide them.
Line 24, /RFSH.
Used to control the refreshing of dynamic RAM. It should be noted that a
refresh cycle is a memory cycle and designers should take appropriate steps. The I
register contents will appear as the top eight bits on the address bus during a
Line 25, /Ml.
Z80 /Ml used to indicate an opcode fetch, also used (in conjunction with
/IORQ) to indicate an interrupt acknowledge cycle.
Line 26, /IORQ.
Used to indicate a Z80 I/O cycle. The port address will be on the bottom eight
address lines (A0 to A7). The top eight will have the contents of the A register on
them. If /IORQ is asserted with /Ml it indicates an interrupt acknowledge cycle and
the Z80 will expect to receive an interrupt vector.
Line 27, /MREQ.
Used to indicate a Z80 memory cycle.
Line 28, /WR.
Used to indicate a Z80 write cycle, asserted in conjunction with /IORQ or
Line 29, /RD.
Used to indicate a Z80 read cycle, asserted in conjunction with /IORQ or
/MREQ. It should be noted that /RD is not asserted during an interrupt acknowledge.
Lines 30 to 45, A0 to A15.
Z80 address lines, should be tristated during a /BUSAK.
Lines 46,47,48, A16, A17, A18.
Optional implementation for extended addressing, should be tristated during a
Line 49, GND.
An additional ground line to reduce system noise. Must be implemented on both
the mother board and on expansion boards.
Lines 50 to 57, D0 to D7.
Z80 data lines, should be tristated during /BUSAK.
Line 58, RSFU.
This line is reserved for allocation at a later date. Please do not use.
Lines 59 60 61 62, INT 0 1 2 3.
Interrupt request lines, used to generate interrupt vectors from devices that
are not capable of generating their own interrupts. These lines would be monitored by
an interrupt controller which would be capable of generating interrupt vectors, the
controller must be capable of being programed with the sense of a particular line
(i.e. whether its active high or active low) and the vector. A device unable to