INMC 80 News


October–December 1981, Issue 5

Page 28 of 71

enable line from IC 2a is also used as the NASIO signal. Although the NAS­COM 2 is fitted with a switch (LSW2/8) to allow either on-board or external ports to be used, as it stands you cannot use both. The NASIO signal provides a means of achieving this, but unfortunately only one signal can be fed to this line (unless you use expensive tri-state logic) as TTL outputs don’t like mixing with each other. So if you intend to use more than one I/O board in the system you must be careful. One way of catering for all eventualities is to use the circuit in Figure 2. Fit this onto one (only) board which uses the bus, switch LSW2/8 to “EXT” and forget about NASIO. There are sufficient unused ICs in the circuit of Figure 1 to build this. If you are using the NAS­COM I/O board, check how it handles NASIO.

Practical details:

Vero Electronics make an 8″ x 8″ copper-tracked perforated card with gold-plated “fingers” (i.e. NAS-BUS compatible) for about #5 (part number 09-0092K) and although not glass-fibre, it does present a cheap alternative to the prototyping boards currently available for DIY circuits, and is more than adequate for this application.

Remember that the NAS-BUS contains lines directly linked to the CPU and other important chips in the system, so be VERY careful of what happens to these lines when they enter your circuit. As a suggestion – letter each track with a felt tip pen as to its function, check and then check again before starting work. Cut any tracks carrying unused signals (NMI, INT, HALT, A8-A15 etc.).

Layout appears not to be critical – refer to a mood TTL primer (eg. TTL Cookbook, Lancaster) if necessary. Check for shorts, tracks still needing to be cut etc. Test the board without the chips and check that all voltages are in the right places. Fit the TTL devices and adjust LSW2/8 to EXT and check that the keyboard still works, if possible check the correct operation of the 2 MHz clock (if you are using the divider circuit) and the BC1 and 8DIR signals with a scope using the following programmes:

Routine to check PSG resister latch:

     LD A,#0F
     JP LOOP

The BC1, BDIR, NASIO and all DATA lines should all give simultaneous positive pulses.

Routine to check data write:

     LD A, #0F
     JP LOOP

The BDIR, NASIO and all DATA lines should all give simultaneous positive pulses, BCl is kept low.

Routine to check data read:

     JP LOOP

BC1 and NASIO should give positive pulses, the data lines will reflect the contents of the addressed resister and BDIR should remain low.

If WAIT states are used, these should be active (low) within the pulses described above.

Page 28 of 71