Micro­power

  

Volume 1, Number 4 – December 1981











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THE ZILOG Z800

by Rory O’Farrell

Zilog have anounced the Z800, a replacement upgrade for the Z80. Information on the new processor is scant, but in a brief press release Zilog claim the following:

Three to five times the performance of the Z80A with comparable speed memory,
On chip internal clock; 12 18 & 25 Mhz,
Expanded instruction set that is binary compatible with all Z80 instructions,
Multiply and divide instructions,
On chip memory management and protection unit,
Direct addressing of half a megabyte of memory (524288 bytes),
Programmable bus timing (wait states selectable in software),
Multiplexed address/​data bus (i.e., address and dasta lines share the same pins) with Z80 bus signals for easy interfacing to Z80 family chips.

It is claimed that the instruction set is more powerful than that of the Z80, and that it incorporates many of the features of the Z8000. The chip can be used with any of the Z80 or Z8 peripheral chips.

The register structure seems to be very close to that of the Z80. There are two sets of registers, each comprising an accumulator, a flag register, and six general purpose registers. Transfer of data between these duplicate sets is accomplished by the use of ‘exchange’ instructions. Zilog claim that the result is a faster response to interrupts, and easy implementation of context switching for multi-user processing. In addition there are the interrupt and refresh registers, and two 16 bit index registers. Two implied stack pointers are available: the system stack pointer (which we know and love?) and a user stack pointer. The CPU mode of operation will determine which of these pointers is used. The user stack pointer will facilitate the writing of very efficient high-level language compilers and interpreters.

The allowable data types are bits, BCD digits (nibbles, 4 bits), bytes (8 bits), words (16 bits), and byte strings up to 64 Kbytes long. The standard Z80 instruction set is extended with 8 and 16 bit multiply and divide, and the SET and TEST instruction. In addition, there is a fourth interrupt mode, which provides more flexibility in handling interrupts and traps. The new CPU has a comprehensive trapping structure, allowing for single stepping, system calls, and privileged instruction traps.

The chip offers programmable bus timing. It can insert, under software control, wait states into both memory and I/O transactions. The on-chip clock can also be programmed – an example is quoted of running 6 Mhz memory from the internal 12












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