esting is quite simple, I found. It’s a matter of Fitting
the WAIT GATE with all the MATTs (Mi and R/W) in operation,
giving a normal and average cursor flash rate. This is followed
by setting to no WAITs, which gives a noticeable change of
cursor rate. A further test of MI WalTs only, gives an increase
in cursor rate, but lees noticeable. (In almost all systems the
NAS-SYS ROM and workspace RAM will work without WAITS). Any
poor connections of the wire wrap sockets will show up as faults
In other sections of the Nascom circuit. These include the RESET
smitth, single sten logic. P10, and serial interface. The manual
eiplains this, and these functions should. be watched during
First operations:
TABLE 1. SWITCH DATA
SWITCH No. BLOCK CYCLE TYPE
1 a «ROM mt
2 & (ROM) Rw
3 B CRAM) mt
4 B (RAM) Rw
TABLE 2. MEMORY DEVICE TIMING
Watt STATE TYPE MEMORY ACCESS TIME
None 2750s
M1 ONLY “400n5
Fut ME RMD “ne
Using the ahove tables, the Latter section of the manual
explains how the switches in Table 1 are used to provide each
ROM and RAM speed sn Table 2. Switches 1 and 2 are set for ROM:
Sand 4 for RAM. Tf an access tine af < 4007s ands 278s. is
required for ROM and” 27Sns for RAM, the switches sould be set:
Fon Ran
‘up 2 pour < DOWN 4 DOWN
Mt OND Ry ONT MNO RW
The main idea behind the WAIT – GATE, says the manual, is:
“In most svstems only snme memory access cycles actually
bent UAIT states. The WATT – GATE circuit orovides a flexible
moans uf controlling WAIT states so. that’ the number of
Wnnereesary WAIT “states is minimised This can result ina
voter ahle increase in GePalle speed. e+.
This 1 must aurew mith, when va consider that by far the most
frequently uae! oner ations, are the reading and writing of the
memeces berth ROM and FAM,