Using this interrupt mode, which is in general known as “Vectored
Interrupt’, we are more or less obliged to use the Z80 family of peripherals to
allow us to avail of the vectoring. It may be possible to use other devices to
the same effect, but this will depend on the device. Zilog
make two families of
peripheral devices. Designed as full members of the Z80 family are the following:
|giving two 8 bit parallel ports
|giving four counter/timer channels
|offering two serial input/output ports, with high speed
|a reduced specification SIO, best thought of as an
|offering high speed transfer of data from port/memory to
memory/port, with search facilities.
In addition to these devices, Zilog also offer another family, the 8500
peripheral device family. These devices are specialised microcomputers, which are
set up to be input/output devices of astonishing complexity! I propose to deal
only with the PIO and CTC at present, as these are the only two devices on which
I can claim any experience. The SIO and DART I may be able to deal with in the
future as Gemini have an SIO board in design. [Ed. – using SCCs from the 8500
family, I believe, not SIOs.] The DMA chip presents problems when using an N1
with Nascom bufferboard, as it becomes necessary to modify the buffer board to
allow the DMA to reach into the 4k block of the standard Nascom.
Let us now park the CPU interrupt handling to one side, and consider
first the PIO. This device offers a number of operating modes. It comprises two 8
bit parallel ports, each with two handshaking or control lines. As normally used,
it appears as a block of four ports, with the data ports A & B, and then the
corresponding control ports CTRLA & CTRLB. On the standard Nascom, this block
occupies Ports 4,5,6,7. Port A is number 4 with its control port CTRLA number 6.
The two data ports are Read/Write, the two control ports are Write only. We can
set this device up in a number of operating modes. First of all, we can pick Mode
0, which configures the port as Output, say driving a parallel printer. The two
handshake lines are used here, one from the PIO to indicate that the data is
ready on its output pins, and the other from the peripheral device to say ‘Thank
you, I’ve got that’. Mode 1 sets the port up as Input, with the handshake lines
working in a similar way. These two modes can be set up on ports A or B, but mode
2 differs. Mode 2 sets up port A to handle bidirectional data. As it now needs
two hand shakes, one for in data and one for out data, we steal the handshake
lines from Port B. So Port B can only be set to Mode 3 if port A is in Mode 2.
Either or both ports can be set to mode 3 at any time – it is not necessary to
have a port in Mode 2. Mode three is the Bit Mode. It allows the eight lines from
the Port to be configured as any combination of Input and Output lines you
require. As well, we may instruct the port to interrupt on simple logical
combination (AND or OR) of some of these lines. We don’t have to use them all for
the interrupt, and can also define whether they should cause an interrupt when
high or when low. There is one restriction – all interrupting lines must be at
the same level.
On first introduction setting the PIO up is so complex, that an example
is perhaps the best way to demonstrate. We will set the PIO up to its four modes
by way of example.
On power up, the PIO enters a reset state. This means that the internal
structures of the PIO are all set to zero, or neutral conditions, as appropriate.
We unfortunately cannot get this effect by hitting System Reset on N1s, as the
PIO hadn’t enough pins to allow for this. Instead, the PIO designers provided
that a reset would be signalled if the PIO received an /M1 signal without /RD or
/IORQ. To obtain this signal, it is necessary for N1 owners to make a small