80-Bus News


January–February 1983, Volume 2, Issue 1

Page 11 of 56

In this, the LSB 4 bits of 0111 indicate Interrupt Control Word. Bits 4 to 6 are only used in Mode 3, and Bit 7 enables or disables the Port to interrupt. If Bit 7 = 1, then Interrupts are enabled. If 0, then disabled. If an interrupt condition occurs while disabled, the PIO latches it, and interrupts as soon as Port interrupts are re-enabled. If we don’t want this to happen, then we can set Bit 4 in the Interrupt Control Word to reset the pending interrupt condition. Bits 4 – 6 are used in Mode 3. If Bit 6 = 1, then selected lines are monitored for AND condition, i.e. they must all be active for interrupts. If bit 7 = 0, then any one of them can be active and cause an interrupt. Bit 5 =1 indicates that they should be monitored for High level, = 0 for low level. Bit 4 = 1 indicates that the next word sent to the port must define a mask. Only those lines whose mask bit is 0 will be monitored for generating an interrupt. To enable or disable a Port interrupt without modifying the rest of the Interrupt Control Word, we write the following word to the port.

EI x x x 0 0 1 1

Problems have occurred with the PIO’s little peculiarities. Disabling interrupts by writing the above control word to the port is subject to them. For example, you write the disable control word to the port. As you do so, an interrupt occurs. The PIO generates an interrupt, and the CPU acknowledges it. By then, the PIO has deciphered the control word and deactivated the interrupt structure. In consequence, the PIO will not place the interrupt vector on the bus at the appropriate time. The CPU will read such a vector, however. As the bus lines are not in a well defined state, this value will be spurious, giving rise to eccentric behaviour of the interrupt structure. The cure for this is to disable CPU interrupts, send the disable control word, and reenable the CPU interrupts. Here is the sequence of instructions:

LD A,03H        ;Disable word
DI              ;Disable CPU
OUT (PIO),A     ;Disable PIO
EI              ;Enable CPU

This causes the CPU to ignore any such spurious interrupts while the PIO is turning its own interrupt structure off.

So much for the actual instructions for setting up the interrupts in the PIO. Now we have to consider what the Interrupt handling routine is to do. Obviously, without knowing the precise form of your peripheral, this is something I can’t deal with in particular, but there are a few points to draw to your attention. First of all, an interrupt automatically disables any further interrupts – not just from the same device, but over the whole Machine, except for the NMI. It is at your discretion when to reenable them. This action will allow higher priority devices to interrupt the service routine currently running. As a rough rule of thumb, timer and floppy disk interrupts are usually accorded higher priority than simple input/​output devices. So, suppose your parallel printer is connected up to a port, and interrupts for more data. Usually a printer has a buffer within it, and a print rate of 60 – 120 chars per sec. So long as the printer has about 100 chars in its buffer, it won’t need any further attention for about a second. This means that we could, for example, allow our CTC to interrupt the printer routine every half second or so with the time. We can only interrupt a routine when it is in a safe state, so we need to have saved any data resulting from the interrupt before permitting another. Reenabling interrupts is done by executing the EI instruction within the interrupt service routine. To lock after the problem of signalling to the lower priority device that the higher priority device that has interrupted it is finished, and that the lower priority unit can now continue with its interrupt service, we have to terminate each interrupt service routine with EI (enable interrupts) if we have not already used it, and a RETI (RETurn from Interrupt). The EI is not acted upon

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