Volume 1 · Number 1 · August 1981

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Waveform Diagrams

2 MHZ Version:

4 MHZ Version:


1,2,3,4 –Different starts of Z-80 access cycle with respect to 1 MHz
–This point in time that the ‘WAIT’ signal is sampled by the Z-80
* –Effect of adding capacitor to extend write access – not normally needed
–This ensures that ‘WAITS’ generated from different sources do not disturb this synchronisation logic.
# –This ‘preliminary pulse on RVSEL has no effect since cycle is not complete, it is during an unused processor access ‘slot’, and there is no corresponding write gate WVSEL
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