Micropower |
Volume 1, Number 1 – August 1981 |
|
|
Page 24 of 33 |
|
|
|
---|
NOTES |
1,2,3,4 | –DIFFERENT STARTS OF Z-80 ACCESS CYCLE WITH RESPECT TO 1 MHZ |
![]() |
–THIS POINT IN TIME THAT THE ‘WAIT’ SIGNAL IS SAMPLED BY THE Z-80 | |
* | –EFFECT OF ADDING CAPACITOR TO EXTEND WRITE ACCESS – NOT NORMALLY NEEDED | |
↑ | –THIS ENSURES THAT ‘WAITS’ GENERATED FROM DIFFERENT SOURCES DO NOT DISTURB THIS SYNCHRONISATION LOGIC. | |
# | –THIS ‘PRELIMINARY PULSE ON RVSEL HAS NO EFFECT SINCE CYCLE IS NOT COMPLETE, IT IS DURING AN UNUSED PROCESSOR ACCESS ‘SLOT’, AND THERE IS NO CORRESPONDING WRITE GATE WVSEL |
|
|
Page 24 of 33 |
|
|
|
---|