must be bent sideways so that they miss the socket, and can be wired to the Bank
Select board. Data bit BS2 and its complement are gated with E000-FFFF from
the MD PROM in a quad OR gate, 74LS32. A logic 0 on BS2 will select XROM
and hence the EPROM block, and a logic 1 will select the Basic ROM (BROM). The
CLR input of the 74LS175 is wired to the system RESET line, ensuring that bank
0 is selected on reset or power-up.
Wiring of the link blocks LKB1 – LKB8 is shown in figure 2. Addresses A10
and A11 are wired from the workspace RAM linkblock, LKB9. Link switches
LSW1/7 and LSW1/8 should be up. Note that the wiring scheme shown is only
suitable for 2732s; Texas 2532s do not have the same pinout.
Fig. 2 LINK BLOCK WIRING FOR 2732 EPROMS
One further complication of this method of bank selection is that the
addresses E000-EFFFH are confined to EPROM block A, and addresses F000-
FFFFH are in block B. This is best explained by the table bellow:
My own system Jumps to D000H on reset, where a menu display and control
program select the required bank and execute at the appropriate address.
Software intended for execution in RAM is copied down to 1000H by the control
Figure 3 shows a suitable vero layout for the bank selection unit. The unit is
shown from the component side.