80-Bus News


July–October 1982, Volume 1, Issue 3

Page 29 of 51


2K 2716 EPROM & 6116 RAM for the Nascom 2 Main Board by J. Rollason

208 es Un Ss Sh the Se he a i AS SN NS SS ls I NS SO ts EE UR ERS HS

Having read E.P.T. Anderson’s interesting article (rinmcs0-5) on installing 2K EPROMs on the Nascom 2, I endeavoured to use the same technique to instal 6116 2K static RAMs but without success. Eventually I had to resort to the last option of actually trying to understand the address decoding on the Nascom 2 in order to come up with an alternative solution to the problem.

I found that it was only necessary to increase the 1K bandwidth pulses from the address Multiplexer Ic46 (CSO – CS7) to 2K and to connect pin 19 of the linkblock to A10 on the address bus.

The resulting solution is simple and flexible and can also be used with 2716 EPROMs requiring no extra components and less wiring than the published solution (without which I would not have attempted this).

The modifications for 6116 Rams are:

1. Wire up the link blocks as for 4118 static RAM except pin 19 which should be connected to A10 available on the link block below the VRAM IC 48 (I prefer to keep all my wiring on the component side of the board).

2. Lift out IC46 and bend out pins 3 and 13 to the horizontal position and carefully solder wires from A12 & Att (available on the linkblock as above) to


%3. Wire the appropriate decode pads as normal on LKS1. Note that since each block is now 8K and not 4K then extra decode addresses will need to be connected to each block e.g. to assign block A to addresses 1000-2FFF would require pins 5, 6, 13 and 14 to be mutually connected.


4. Switches LSW1/7,8 both need to be down (Open)

If 2716’s are required then the Link block should be configured as in the diagram.


_ fo do this it is necessary to pull pin 18 to +5 volts using a 1K resistor. The appropriate chip pulse can then be switched to or from the relevant chip without the chip enable causing spurious read/writes to occur. If it is only desired to select Block A instead of Block B or external memory /Block A or B, then it is only necessary to switch the address decodes on LKS1 to the appropriate RAM/ROM selects on pins 1 to 8 (or to open circuit).


Note that “even” 4K blocks (e.g. 2000, 4000 etc.) will normally occur on the lower 2 chips in each block, whereas odd 4K addresses will occur on the upper 2 chips i.e. it is not possible to select two odd addresses to the same block (e.g. B000 & D000). This should not be a problem. Note !!! Pin 9 on LKS1 is for EH000-FFFF, not E000-EFFF as claimed!


A he Ne A HN a So

It appears that the same technique could be applied for 4K chips, in which case pins 3 & 13 of IC46 would be connected to A13 & A12.

This is an OCR’d version of the scanned page and likely contains recognition errors.

Page 29 of 51