80-Bus News


July–August 1983, Volume 2, Issue 4

Page 21 of 55


In the last issue a brief summary of the I/O ports currently occupied by 80-BUS/​Nasbus compatible boards was given, along with a request for any corrections to this and for any information on products not included. The following paragraphs are extracts from various letters received in response to the above request. Thanks to all concerned.


Doctor Dark writes: “Only two I/O ports are required for communication with Pluto. The ports have consecutive addresses that may be selected to be on any 20H byte boundary. Pluto decodes 4 addresses, two of which are not used, but are reserved for future use. Pluto is pre-configured with a base address of A0 hex. This can be changed to any of 00, 20, 40, 60, 80, C0, or E0, all of which are in hex, of course. For compatibility with Nascom systems a NASIO signal is optionally provided by Pluto. Only one board in the entire system should provide this signal which is asserted when an IO address for the Nascom main board is decoded. If this signal is to be provided by Pluto then the points marked NASIO should be linked. Pluto asserts this signal for all addresses from 00 to 7F hex inclusive which means that all peripheral boards (including Pluto) should use I/O addresses above 80 hex. The Nascom Internal/​External I/O addressing switch must be set to enable external addressing. For compatibility with Nascom 1 systems, a DBDR option is provided by linking the points marked.”

Graphics Board

Mr R. E. Moyle writes: “You may not be aware of S. Holmes’ Graphics Board. This board uses ports 8 – 31 to control a Texas Colour Graphics chip, two sound generators, a RTC, CMOS scratchpad memory and eight ADCs. Unfortunately the board is not fully 80-BUS compatible as it omits the “obsolete” signals and daisy-chain protocols. These are easily added, however, and moving the I/O addresses to 32 – 63 is also simple.”


CHS Data Sciences write: “We have produced a board which:

a) has 16K of CMOS RAM and a Real Time Clock which also detects power up/down and reset conditions.

b) standard I/O address is D0-D3, no alternative is suggested until such time as an I/O map is produced, the link selectable header plug may be changed for any contiguous block of 4 on a boundary of 4, paged memory is also on port FFH.

c) NASIO and DBDR are provided from open-collector gates with NASIO also being link selected

d) the board is fully Nasbus 4 compatible

e) the memory is page selected by port FFH, additionally it will always be selected on page 0 (selected by reset) regardless of page switch setting, this ensures that the board controls power up/down and ‘manual’ resets

This board does not use the National Semiconductor Real Time Clock and so it does produce the Year Date, the clock is supplied via a on-board battery so maintaining clocking integrity.”

IO Research A/D Board

J. Da Silva Alvoeiro writes: “I have one IO Research A/D Convertor Board and it uses ports 20-23, NOT 30-33 as described in your magazine.”

This is an OCR’d version of the scanned page and likely contains recognition errors.

Page 21 of 55