80-Bus News

  

May–June 1984, Volume 3, Issue 3











Page 12 of 51











A7 and A15 to provide the additional RAM address line A7’, and find some other means of generating /CAS. Therefore A7 is removed from IC20-pin3 and taken to IC21-pin 13 and the connection to earth removed; A15 is picked up from IC25-pin 16 and taken to IC21-pin 14, and the 4K7 resistor removed. The complete set of 16 address lines are then multiplexed by IC20 and IC21.


(a)


(b)

FIGURE 2

Now we have to produce a /CAS signal with an appropriate delay to replace the one generated by the multiplexer. There are various ways in which this could be done but an elegant solution, using only a single 74LS74, was shown recently by D. Allen (3). His circuit is shown in Fig. 2(b), and the relevant part of the original RAM A circuitry in Fig. 2(a). The latter uses only one half of the 74LS74, but by rewiring IC21 to the form of Fig. 2(b) both /CAS and the switch signal SWMx for the multiplexer can be generated. This works as follows: when /MREQ and /CS go low, /RAS is generated, thus latching the row address A0 to A7. At the same time, the reset line of both flip-flops goes high. The D input is /REF, which is high during memory access cycles, and so on the first positive edge of the system clock after /MREQ, IC21(b) flips, which switches the A8-A15 to the RAMs. On the next negative going clock edge, IC 21(a) flips /CAS low, latching the column addresses. During refresh cycles, the D input to both flip-flops is low and so neither switches and /CAS remains high, although /RAS goes low to strobe the row addresses providing refresh.

Fig. 3 shows waveforms derived from my modified board using the shortest program I know which is xx: JR xx in assembler, or 18 FE in hex. When loaded anywhere in memory, this program repeatedly accesses that address. The waveforms were obtained with an 8-channel Tektronix 7D01 Logic Analyser with a time resolution of 20 nSec. Two complete cycles are shown; note the sequence of the /RAS, SWMx and /CAS signals and how the A0 line toggles during each refresh period. In this arrangement, /CS, which is applied to either P6 or P7 depending upon which block of sockets is used, can, in principle, be tied to earth; however, see below. Also, the 74LS32 OR gate, which drives the 74LS74 flip-flop reset-pin high when either P6 or P7 and /MREQ are low, is not












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