Scor­pio News


July–September 1987 – Volume 1. Issue 3.

Page 43 of 67

The Theory

The theory starts with the 256k chips being pin compatible with 64k ones except that pin 1 is now used as A8 (the additional address line necessary to address all the extra memory) By connecting this A8 via a multiplexer to A16 and A17 it should be possible to address the whole of the 256k. It doesn’t matter that A8 on the RAM chip should be multiplexed between A8 and A17 bus address lines and all the other address lines moved up to match as it is not necessary to use consecutive cells in the RAM, the only requirement being to ensure that the same location is addressed consistently.

Looking at the circuit diagram revealed that I would still only be able to the lower 64k as the chips are only selected when the top three address are all zero. Working backwards from the PAL, through which all onboard addressing is done, the onboard RAM is selected via AEO (pin 18) which is high whenever A16 – A13 are all low (i.e. the address is in the lower 64k bytes). To select the onboard RAM for any address within the lower 256k bytes, AEO has to go high regardless of the state of A16 and A17 so it becomes the inverse of A18. Unfortunately the signal AEO is also used to determine when the boot EPROM is selected as this is expected to be at 0F000H – 0FFFFH. The way round this is to sever the connection between A16 – A18 and AEO, leaving Al6 &ndash A18 to be used to select the EPROM and take A18 via an inverter to AEO on the PAL to select the onboard RAM.

The Modifications

Now to the actual modifications (refer to diagram) The first step is to remove the eight 64k bit RAMs from their sockets (ICs 8,11,17,18,25,31,32,38). Very carefully take the eight 256k bit RAMs and bend up pin 1 on them all. Then insert them into the sockets making sure that they are the correct way round. On my board, manufactured in 1983, all the RAM chips were socketed making this step very easy. However, photographs in the current Gemini catalogue show the RAM chips soldered directly into the board which means a lot more work for some people. Wire all the lifted pins together and to earth which I found at a post near IC43. Then check that the board still works before proceeding.

The second step is to take a new 74LS257A quad multiplexer chip and bend up pins 2 – 7 and 9 – 14. Then solder it directly above IC 43, also a 74LS257A, with the same orientation so that it can pick up power and some control signals from it (i.e. pins 1, 6, 15 and 16 are all soldered onto the same pins on the chip below). Unsolder the wire from the earth pin connected in step two and solder it to pin 9 of the new 74LS257A. Connect pin 10 to Al6 which can be conveniently found near the edge connector, and pin 11 to Al7 which is next to Al6. Now check the board before proceeding.

The last hardware modification is to enable all the memory to be addressed. Take a new 74LS04 hex inverter chip and bend up pins 1 – 6 and 8 – 13, then solder it above IC 27 (the same way round) connecting the power pins 7 and 14 to the chip below. Solder pin 13 to Al8 (next to Al7 near the edge connector). Carefully remove the PAL chip, IC 26, and bend up pin 18 and replace it in its socket. Connect this pin to pin 12 on the new 74LS04 and check that the board still works before finally closing up the case.


When it comes to using the mapping registers, these can be altered by use of the Z80 OUT instruction “out (c),r” where the memory mapping port (0feh) is in the “c” register and during execution, the “b” register contents are also placed on the address bus where the most significant four bits select the mapping register. The “r” register contains the 4k block number 0 – 07fh which is written into the mapping register. The boot EPROM ensures that the mapping registers are initially set up to map the bottom 64k bytes in a one to one mapping (i.e. the registers contain 00h, 01h, 02h, up to 0fh).

Page 43 of 67