Scor­pio News


July–September 1987 – Volume 1. Issue 3

Page 43 of 67

The Theory

The theory starts with the 256k chips being pin compatible with 64k ones except that pin 1 is now used ae Ad (the additional address line necersary to Sdirees all the extra memory) By connecting this AB via « multiplexer to Als and Al? ££ should be possible to address the whole of the 236k. It doesn’t Batter that AS on the RAM chip should be multiplexed between A® and Al? bus Address lines and all the other address lines moved up to match as it is not heceseary to use consecutive cells in the RAM, the only requirement being to Gnsure that the same location 1 addressed consistently.

Looking at the circuit diagram reveled thet I would atill only be able to the lower 64k as the chips are only selected vhen the top three address

‘are all. zero.” Working backwards crom the PAL. through which all onbosrd addressing is done, the onboard RAH Je selected via AEO (pin 18) which is high Whenever A16 – A13 are all low (1. ie in the Lover Suk bytes) To Gelect the onboard RAM for any lower’ 256k bytes, AEO has to go high regardless of the state nd AL? go it becomes the inverse of AB Unfortunately the signal AEC {e alee used to determine when the boot EPROM is selected as this is expected to be at 0F000H – 0FFFFH. The vay round this is to Sever the connection between A15 A18 and A20, leaving Ale AS to be used to Select the EPROM and take A18 via an nverter to AEO on the PAL co select the onboard RAM.

The Hodifiestions

Now to the actual modificatfons (refer to diagram) The first step is to remove the eight ik bit RAMs from their sockets (ICs 8,11,17,18,25,31,32,38) Very carefully take the eight 256k bit RAMs and bend up pin i on them all ‘Then insert them into the sockets making sure that they are the correct vay round on my board, ‘manufactured in 1903, ail the RAM chips were socketed making this

‘ia the current Gemini catalogue show the

The second step Ls to take a new 7415257A quad aultiplerer chip and bend up

: ‘then solder it directly above 1c 43, also a 74152574, ‘oteneation so that it can pick up power and tome control. signals From it (lee. ping 1; 6, 25 and 16 are all soldered onto the same pins on the ehip below). Unvolder ‘the wire from the earth pin consected in step two and Solder it to pin sof the sev T6Lsz57A Connect pin 10 to Alo which can be Conveniently found sear the dge connector, and pin a1 t0 Al? which 1a next eo Aer “Now check the board before proceeding,

‘The last hardware modification is to enable all the memory to be addressed. Take 2 new 76L508 hex inverter chip and bend up pins I- 5 and B= 13, then solder ft above 1c 27 (the seme way round) connecting the power pins 7 and 14 to the chip below Solder pin 13 to A18 (next co Al? near the edge connector). Carefully remove the PAL chip, 1628, and bend up pin 18 and replace Tt in tt socket. Connect this pin to pin 12 cn the new 74L804 and check that the board SELII works before finally closing up the case

Software When it comes to using the mapp by a of the £80 OUT instruction ‘out (c).e” where the memory mapping port (Ofeh) is

in the *e* register and during execution, the *b” register contents are also placed on the address bus where the most significant four bits select the sapping register. The *r” register contains the 4k block number 0 – 07th which Is written into the mapping register. The boot EPROM ensures that the mapping registers are initially set up to map the bottom 64k bytes ina one to one mapping (i.e the registere contain 00h, Ol, 02h, up to Ora)

This is an OCR’d version of the scanned page and likely contains recognition errors.

Page 43 of 67