|A) S1A. Position||1: VWRAM to 0800H for NAS-SYS with 48 x 16 screen.|
|2: VWRAM to F800H for CP/M with 48 x 16 screen.|
|3: VWRAM disabled.
card in use.|
|B) S1B. Position||1: VIDEO O/P socket selected to NASCOM 2 by relay.|
|2: As position 1.|
|3: VIDEO O/P socket selected to IVC card by relay.|
|C) S1C. Position||1: RESET JUMP to 4000H to ‘boot’ NAS-SYS.|
|2: RESET JUMP to 2000H to ‘boot’ CP/M.|
|3: As position 2.|
|LSW1/1 and LSW1/4||Up|
|LSW1/2 and LSW1/3||Down|
The arm of S1A should be connected to LKSI pin 2.
Pole 1 to LKSI pin 15.
Pole 2 to LKSI pin 13.
The arm of S1C should be connected to common negative.
Pole 1 to LSW1/2 pin 19 (or IC2 pin 6).
Poles 2 and 3 to LSW1/3 pin 18 (or IC2 pin 13).
S1B is unnecessary if no
card/VIDEO monitor is used.
(N.B. From chats with other N2 owners it is clear that quite a few do not
realize that it is quite permissible to use 64K of RAM and to overlap this
with RAM or ROM located on the CPU card. The NASCOM 2 produces a signal that
disables any RAM external to the CPU card that is decoded at the SAME address
as RAM or ROM on the CPU card. BUS conflict is thus avoided. It would
therefore be quite in order to insert even more ROM’s onto the N2 card and to
access these by extra switching.)
A few points that may be of interest:
Memory test. The test that I use is the one supplied with the
RAM cards. A full assembly listing was supplied with RAM B (the assembly was
correct but there was an error in the HEX listing that I received). This test
is very quick and useful but there is a snag. It will not run with NAS-SYS in
RAM as it stands. (The one with the 64K RAM card had the ‘bug’ removed –
Ed.)The reason for this may be found near the end of part 1 of the test. At
location 0CD9H is an LDI instruction. This moves bytes pointed to by HL to the
location pointed to by DE, whilst counting in BC. In the memory test, DE is
not being used for anything relevant at this time, but it is pointing to low
memory. When NAS-SYS is in ROM no ill effects occur, but when it is in RAM it
gets corrupted and as soon as the program reaches the RST PRS at 0CDEH
‘CRASH’. The problem may be resolved by removing the LDI and replacing it