80-Bus News

  

May-June 1984, Volume 3, Issue 3











Page 18 of 51











18

The SVC offers a variation on this theme. For various reasons the screen memory word width remains at 8 bits. This, as before, leaves a single bit that can be used as an attribute bit. But the SVC, unlike the IVC, allows this bit to select a variety of attributes. So setting bit 7 of a character can select one or more of the following attributes:- use the alternate character generator, blink the character, half intensity character, and, display the character with a half-tone background. Note that I said “one or more”. The SVC supports an escape sequence that is used to select which attributes you want. You can select any combination of the above, eg. blink + half-intensity, but the one thing to remember is that with only one attribute control bit available, all characters on the screen with this bit set will respond in the same way. Therfore it is not possible to have inverse characters on one part of the screen, and half-intensity characters on another part.

One apparent omission from the attribute list above is that of inverse video. This was originally included as a specific attribute, but was later dropped in favour of the half-tone background. It is assumed that inverse video is provided in the usual way via the alternate character generator.

TRANSPARENT ACCESS & ESP

With the SVC, a hardware technique is used to achieve transparent access. On the face of it all that has to be done is to connect the “display enable” (or -display active’) signal from the display controller via a few gates to the Z80 /WAIT input. Thus, if the processor attempts to access the screen memory while the display is active, it is made to wait until the end of the display period, after which the Z80 is free to continue with its read/write cycle. However a problem arises when the Z80 finds, on going to access the display memory, that the display is inactive. The dilema here is that although the display memory is free at that instant, the display controller may start a new display line at any moment (like in the middle of the forthcoming read/write cycle of the Z80). If it does, this will lead to one of two outcomes: a corrupted read/write cycle, or interference down the left hand side of the display depending on which controller gets priority.

This is where ESP comes in. The arbitration circuit has to know whether there is time for the Z80 to complete its read/write cycle without interruption, or whether the /WAIT signal should be applied immediately as the display controller is about to start a new display line. Those of you who have followed the description so far are probably thinking – -ah! you just generate or tap off an earlier version of the Display Enable signal and use that”. Unfortunately this is easier said than done as the “display enable” signal generation circuits are buried deep inside the 40-pin plastic package of the display controller and only the final signal emerges on one of the pins. (That’s what modern LSI does for you!) There is a way around this problem and that is to apply a classic wartime (and peacetime) ploy of mis-information. What happens with the SVC is that some external delay has been added to the “Display Enable” signal, and in setting up the internal registers of the controller, the SVC monitor informs it that the first address of the display is a byte earlier than in fact it is.

The following simplified description assumes a screen format of 80 x 25: When the display controller displays a TV line it loads its display memory address register with the starting address of where the current line of characters is stored in the memory (lets call it N). The address register is then incremented at the character rate for the entire TV line width (64uS)


This is an OCR’d version of the scanned page and likely contains recognition errors.











Page 18 of 51