80-Bus News

  

January–March 1982, Volume 1, Issue 1











Page 17 of 55











RTC Board

NASCOM REAL TIME CLOCK AND CALENDER

by J. R. Williams

National Semiconductor MM58174

The National Semiconductor MM58174 is a CMOS real-time clock and calender chip in a 16-pin DIL package which is easily interfaced to the Nasbus. This device incorporates 4-bit registers from which the CPU can read, as BCD digits, the time from 1/10ths secs. to tens of hours, the day of the week, and the date from days to tens of months. The on-chip oscillator is controlled by a 32768 Hz crystal and timekeeping can be maintained by a backup battery when the 5V supply is switched off. In addition, the MM58174 provides a facility for generating CPU interrupts at intervals of 0.5 sec, 5 sec or 40 sec.

Interfacing ta Nascom

The circuit used by the writer to interface the MM58174 to his NASCOM 1 is shown below. The circuit was assembled on a Vero DIL prototyping board which plugged into a spare 80-way connector on the NASBUS. Bus timing was not a problem with the NASCOM 1 which runs with a 2 Mc/s clock and should still be acceptable with the 4 Mc/s clock of the NASCOM 2 provided that the 500ns MM58174N is used.

Addressing

The clock chip is interfaced onto the bus occupying 16 I/O port addresses (20H to 2FH in the writer’s system), The bus address lines A0 to A5 connect to the clock register address input pins AD0 to AD5. The upper I/O address lines A4 to A7 are decoded by a 7ALS145 to select addresses in the range 20H to 2FH. The clock chip is selected when an address in this range coincides with IORQ.

Data input/output

The clock’s data I/O pins DB0 to DB3 connect to the NASBUS data I/O lines D0 ta D3. The NASBUS RD and WR lines connect directly to the MM58174’s NRDS and NWDS pins. The NAS data bus is switched to the read direction by pulling DBDR down when the clock chip is read by the CPU.

Interrupt Control

Additional logic is included ta enable the MM5174’s interrupt facility to be used. When the clock’s interrupt output goes low, an interrupt is initiated provided IEI is high – i.e. no higher priority interrupt is active. While either the clock interrupt or a higher priority interrupt is active, IEO is held low to inhibit any lower priority interrupts.

Operation in the Z80 interrupt mode 2 is provided for by pulling all eight data lines down to return a zero interrupt vector (i.e. 00H) in response to the CPU’s interrupt acknowledge (IORQ active with M1). Simultaneously, DBDR is pulled down to switch the data bus to the read direction.

All this logic can, of course, be omitted if the interrupt facility is not needed.


This is an OCR’d version of the scanned page and likely contains recognition errors.











Page 17 of 55