80-Bus News

  

January-March 1982, Volume 1, Issue 1











Page 17 of 55











7

RTC Board

NASCOM REAL TIME CLOCK AND CALENDER by J. RB, Williams

National Semiconductor MM58174

The Mational Semiconductor MM58174 is a CMOS real-time clock and calender chip ina ie-pin DIL package which is easily interfaced to the Nashus. This device incorporates 4-hit registers from which the CPU can read, as BCD digits, the time from 1/10ths secs, to tens of hours, the day of the week, and the date from days to tens of months, The on-chip oscillator is controlled by a 32748 Hz crystal and timekeeping can be maintained by a backup battery when the 3V supply is switched off, In addition, the MM52174 provides a facility for generating CPU interrupts at intervals of 0,5 sec, 5 sec or 40 Secs

Interfacing ta Nascom

The circuit used by the writer to interface the MM96174 to his NASCOM i is shawn below, The circuit was assembled on a Vero DIL prototyping beard which plugged into a spare €0-way connector on the NASBUS, Bus timing was not a problem with the NASCOM i which runs with a 2 Mc/s clock and should still be acceptable with the 4 Mc/s clock of the NASCOM 2 provided that the S00ns MM5S174N is used,

Addressing

The clock chip is interfaced onto the bus occupying 14 1/0 port addresses (20H ta 2FH in the writer’s system), The bus address lines AO to AS connect to the clock register address input pins ADO to ADS. The upper I/O address lines A4 to A? are decoded by a 7ALS145 to select addresses in the range 2OH to ZPH. The clock chip is selected when an address in this range coincides with IORG,

Data input/output

The clock’s data I/O pins DRO to DBS connect to the NASBUS data I/O lines DO ta DG. The NASBUS RD and WR lines connect directly to the MM5S174’s NRDS and NWDS pins. The NAS data bus is switched to the read direction by pulling DBDR dawn when the clock chip is

read by the CPU.

Interrupt Contral

Additional logic is included ta enable the MM174’s interrupt Facility to be

used. When the clack’s interrupt output goes low, an interrupt is initiated provided TEI is high – i.e. no higher priority interrupt is active, While either the clock interrupt or a higher priority interrupt is active, IEO is held low to inhibit any lower priority interrupts.

Operation in the Z80 interrupt made Z is provided for by pulling all eight data lines down to return _a zero interrupt vector (ie, OOH) in response to the CPU’s interrupt acknowledge (ORG active with Ml). Simultaneously, DBDR is pulled dawn to switch the data bus to the read direction.

All this logic can, of course, be omitted if the interrupt facility is not needed.


This is an OCR’d version of the scanned page and likely contains recognition errors.











Page 17 of 55