80-Bus News


January–March 1982, Volume 1, Issue 1

Page 18 of 55


Fower supply

When the NASCOM 5V supply is available, the clock chip runs with Vdd=5V via TRi. Itis important that this arrangement, rather than a simple diode, be used to ensure that Vdd is Close enough te the SV supsly to ensure that an input which is pulled up to SV does not exceed the MM55174’s maximum input voltage rating of Vdd+0.2V,

Standby power (OuA approx.) is provided by a pair of AA-size NiCad cells. These are trickle charged via Ri when the SV is available.

Clock chio operation

For full information on how the MM58174 is controlled, see the NS data sheet (Feb, S06 or later issue), However, it may be useful to note the Fallowing points!

1. Data-change flip-flop operation.

Whenever the data registers are updated – i.e, at 0.1 sec intervals when the clock is running – a data change flip-flop is set. This causes the data value "1111" G.e, NmE")

to be output at the next attempt by the CPU to read a data register, This informs the CPU that a data change has occured and also resets the flip-flop so that the new data can be read by subsequent CPU input instructions.

2. Clock counter errors,

When testing the MM52174, the writer encountered a problem of counting errors in the clock’s 0.1 sec. counter and, less frequently, in the seconds counter, These caused the clock to gain up ta 1 mins per hour when under test although it kept good time when running on the NiCad battery with the computer switched off, Investigation eventually revealed that this problem was related to the frequency with which the CPU read the data registers.

The test program being used when the above problem was found read the Oi Sec. register repeatediy while testing for an "-F" data value indicating a data change. This meant that the register was being read perhaps 30,000 times per sec. With a modified version of the test program which tested for the "-F" condition at intervals of Ome, clack counter errors were no longer detected.

3. Interrupt operation.

Interrupt operations are controlled via the interrupt register, First, the interrupt system is must be initialised by outputting zero to this register, follawec by three input instructions to condition the interrupt logic. The required interrupt timing period will then start when an appropriate non-zero value is output to this

register. For example, the data value "1001" (i.e, 9) will initiate a repeated 0.5 sec interrupt.

In order to reset the clock’s interrupt output, the interrupt servicing program must read the interrupt register. A second input from this register is required to condition the interrupt logic and a third to restart the interrupt timer if in the repeated interrupt mode.

An irritating feature of the interrupt system is that, even with immediate servicing of a repeating 0.5 sec interrupt, the interrupts actually occur at intervals of 514.4 ms.

This is an OCR’d version of the scanned page and likely contains recognition errors.

Page 18 of 55